Supercapacitor IC

Approach: The charging path is initially enabled by a pin coming from our microcontroller: RX_MISO_D0 . Which is a pulse wave monitor coded to alternate between high and low, (0 to 3.3V). We code the output to operate at a frequency that allows enough time for the supercapacitor to fully charge, which plugs into the PMOS2 in series with the path. Once the PWM outputs a low, the path is enabled. For charging we use the LM134H: a dedicated constant current source chip. The chip is driven by 5VA and delivers a fixed current directly into the supercapacitor. The output current is set entirely by a single external resistor: I = 67.7mV / R_SET. With R1 (6.67kΩ), this gives I = 67.7mV / 6670Ω ≈ 10µA.

What makes this chip well suited for the task is that it internally adjusts its output to compensate for whatever resistance the path presents as its voltage rises during charging. It samples the voltage and uses internal feedback to maintain a constant current regardless of deviations in path resistance.

However, this behavior introduces a risk: once the supercapacitor is fully charged, the LM134H can drive the supercapacitor voltage above its rated limit. To prevent this, the LM193 comparator monitors the supercapacitor voltage against a 3V reference(max the supercapacitor can take). If the capacitor voltage exceeds 3V, the comparator output floats, which is pulled up to 3.3V by a pull-up resistor, opening the gate of the PMOS1 in series with the charge path and cutting off current. Below 3V, the output is pulled low, keeping the PMOS conducting.

Since the LM134H relies on an external component model that KiCad's SPICE engine cannot simulate directly, running a transient analysis on the schematic produces no result. To validate the behavior, the LM134H is swapped out for an IDC set to output 10µA. This lets us confirm that a 10µA source will behave correctly with the rest of the circuit before committing to the real chip.

Approach: The discharge circuit is built around an op-amp feedback system that forces a constant 10µA from the supercapacitor regardless of how its voltage changes over time. The key insight is that a constant current discharge causes voltage to drop linearly.

NMOS1 connects directly to the microcontroller through a connector pin TX_MOSI_D1, which is coded as a pulse wave monitor that enables the discharge path when high. The current is set by R7 (9kΩ). With a 0.1V reference, the target voltage across R7 is 0.1V, giving I = 0.1V / 9kΩ ≈ 11µA ≈ 10µA (with NMOS propagation delay). TSZ901ILT2 is an op-amp that compares this 0.1V reference against the actual voltage developing across R7 and drives the gate of NMOS2 to correct any deviation: if current rises, NMOS2 is turned down; if it falls, NMOS2 is turned up. This feedback loop is what maintains constant current and ultimately produces a linear voltage decrease.

Approach: To determine how the supercapacitor retains capacitance and resistance in stratospheric conditions, we must record the voltage and current through the path during each cycle and report these values back to our microcontroller (STM32). These analog signals are stored to flash to log all experimental data.

Current monitoring: For current monitoring, we use the INA190 bidirectional current sense amplifier. It introduces minimal voltage drop into the path and outputs an analog voltage proportional to current, which the STM32 converts to a digital reading.

R3 (6kΩ) is the shunt resistor, sized by the expected voltage drop: V = I * R, so 60mV = 10µA * 6kΩ. The INA190 reads the differential voltage across IN+ and IN-, multiplies it by a gain, and adds it to a reference voltage. The 1.65V reference is generated by a TSZ901ILT3 op-amp buffer configured with equal resistors (R5/R6 = 10kΩ each), centering the output at half of 3.3V. This reference is necessary because the INA190 is bidirectional: positive current produces a reading above 1.65V and negative current produces a reading below. Without it, negative current would collapse to 0V and produce unusable data.

The output equation for IN1 is: Vout = Vref + (Gain * Vsense) = 1.65 + (25 * 60mV) = 1.65 + 1.5V = 3.15V (at +10µA) = 1.65 - 1.5V = 0.15V (at -10µA). We selected the INA190A1 variant for a gain of 25.

A DNP (Do Not Populate) low pass filter is included on the output to suppress noise if needed after testing. Because the output reaches 3.15V and the STM32 ADC accepts up to 3V, we step it down with a voltage divider: V_IN1 = Vout_INA * (10k / 11k) = Vout_INA * 0.909.

Voltage monitoring: For voltage monitoring, we use the OPA333 op-amp in unity-gain configuration. It reads the supercapacitor voltage and presents it as a signal to the STM32 via IN0. As with current monitoring, a DNP low pass filter is included if fluctuations appear during testing, and a similar voltage divider steps the signal down to stay within the 3V ADC limit.

Since neither chip is in the KiCad library, both symbols and footprints were created manually from their datasheets. Simulation is not possible without a KiCad SPICE model, so measured values will be validated during post-fabrication thermal testing.

Approach: To read current and voltage values for each GCD cycle, we connect our analog outputs and PWM inputs through the SM12B-GHS-TB, a 12-pin connector. It is powered by 3.3V and 5VA. Since neither input has a dedicated power output pin on the connector, we implement PWR_FLAG symbols to satisfy the ERC. In case something on the experiment card shorts, a fuse on each power input protects the microcontroller between boards. IN0 and IN1 are the voltage and current monitoring pins, received as inputs from the experiment card. RX_MISO_D0 and TX_MOSI_D1 are the PWM control pins driven from the microcontroller. Rather than sharing a single PWM pin for charge and discharge, using separate pins with a slight delay between them eliminates the risk of both paths being active simultaneously, preventing clock-edge shorting. In the high-impedance state, RX_MISO_D0 is pulled high by a resistor, keeping the charge circuit inactive, and TX_MOSI_D1 is pulled low, keeping the discharge circuit inactive.

The schematic also includes decoupling capacitors at the power inputs to every chip. These filter transient voltage fluctuations and ultimately reduce noise on the supply lines to our components.

Approach: Before routing, we run the Electrical Rules Check (ERC) to verify the schematic is correct: pins routed to the right power rails, no floating inputs, no duplicate references, and all footprints assigned. Passing ERC with 0 violations is a prerequisite before moving to PCB layout.

All components have footprints either pulled from the KiCad library or created manually. Our supercapacitor holder is an example of a custom footprint, built by a team member from the physical dimensions of the actual physical supercapacitor holder.

PCB routing connects all power nets to their respective supply pins and GND pins. Decoupling capacitors are placed as close as possible to each chip's supply pin to minimize noise. Once routing is complete, a Design Rules Check (DRC) verifies no layout violations exist.

Approach: My role has been designing and integrating all subcircuits into a single schematic and walking teammates through the design decisions. Experiment card V1 has been fabricated and is ready for component population and testing. With the semester ending, hardware assembly will be handled by team members remaining at Georgia Tech over the summer. In the meantime, I am shifting focus to STM32 firmware, primarily the PWM control logic for charge and discharge cycling. In July, the team will integrate the finalized boards and supercapacitor onto the HASP payload, which will take flight in August.

Since this project is run through Dr. Ready's lab at the Georgia Tech Research Institute, our team had the opportunity to present our research and findings to an audience of United States Space Force, including Chief Master Sergeant John F. Bentivegna and other active-duty members. Presenting work that may one day be used in space applications to the people who operate in environment was an experience unlike any other.